High leakage current is becoming a significant contributor in power dissipation of CMOS circuits whenever threshold voltage, channel length and gate oxide thickness are reduced. Threshold voltage__ampersandsignnbsp;scaling, results in the substantial increase of sub threshold leakage current. To maintain reasonable short channel effect (SCE) immunity, while scaling down the channel length, oxide thickness has to be reduced in proportion to the channel length. But, decrease in oxide thickness results in increase in the electric field across the gate oxide. In this review paper, attempts are made to analyze the previously published works in the specified area. Some of the power optimization techniques have been verified with 16nm Silicon On Insulator (SOI), High K Dielectric, Strained Silicon Predictive Technology Model (PTM) files in ISCAS C17 benchmark circuit.