In this paper, an error-compensated adder-tree is proposed to deal with the truncation errors by performing shifting and addition operations in parallel thus achieving low-error and high-throughput discrete cosine transform (DCT) design. The Discrete Cosine Transform is a type of Image Transform which expresses a sequence of finitely many data points in terms of a sum of cosine functions at different frequencies. The proposed scheme incorporates 9-bit distributed arithmetic (DA) - precision for this work instead of the 12 bits in the previous works, so as to meet the desired peak-signal-to-noise-ratio (PSNR). Thus, an area efficient DCT core is implemented to achieve 1 Gpels/s throughput rate for the PSNR requirements outlined in the earlier works.